The present invention relates to a semiconductor device, and more particularly, to a power fluctuation inhibiting device for inhibiting power supply voltage fluctuation of a semiconductor device.
Due to the higher integration and higher operation speed of recent semiconductor devices, a plurality of digital circuits are synchronized with each other at high speeds. More specifically, a plurality of CMOS circuits in the digital circuits are synchronized with one another so that through current simultaneously flows in the CMOS circuits. This increases the peak value of the through current and increases power supply voltage fluctuation. As a result, the digital circuits, which are activated by the same power supply, may function erroneously. Alternatively, errors in the output signal of an analog circuit may increase and noise may be produced. Fluctuation of the power supply voltage caused by through current must thus be inhibited.
FIG. 1 is a waveform diagram illustrating a prior art example of a method for inhibiting power supply voltage fluctuation by using clock signals with different phases to inhibit fluctuation of power supply voltage caused by through current.
When a plurality of digital circuits are operated in synchronism with a clock signal CLK11, a noise n1 is produced in synchronism with the rising edge of the clock signal CLK11 in a power supply V1. After voltage decreases due to the through current resulting from counter electromotive force produced by an inductance component of a power supply line and negative feedback of a power supply circuit, the noise n1 increases the voltage. In such a manner, when a plurality of digital circuits are driven by the same clock signal CLK11, through current is synchronously produced. This increases the peak value of the noise n1.
When the digital circuits are divided into those driven by the clock signal CLK11 and those driven by a clock signal CLK12, for example, different noises n2 and n3 are produced in the power supply V1. In this case, the dividing ratio of the circuits is 1:1.
Japanese Laid-Open Patent Publication No. 11-308109 describes the above technology.
In the above prior art technology, the different phases of the clock signals inhibit the peak fluctuation value of the power supply voltage. However, when the number of noises produced in the power supply V1 increases, the peak inhibiting effect decreases depending on the dividing ratio of the circuits. Accordingly, the reduction of the noise produced in the power supply V1 cannot be ensured. Further, noise resulting from the power supply noise would still be produced in circuits operated in accordance with the power supply V1.
The peak value of the noise produced in the power supply V1 must be measured by a spectral analyzer or a digitizer. However, it is difficult to measure and confirm the inhibiting effect of the power supply voltage fluctuation obtained by using clock signals with different phases when dividing circuits and setting phases to effectively inhibit the peak value of the noise.